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Synchronous Buck Power Supply Controller
POWER MANAGEMENT Description
The SC1470 is a single output, constant on-time synchronous-buck, pseudo fixed frequency, PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and fast dynamic response with no minimum on time. The excellent transient response means that SC1470 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. At light loads, Power-Save Mode enables the SC1470 to skip PWM pulses for better efficiency. The output voltage can be adjusted from 0.5V to VCCA. The integrated gate drivers feature adaptive shootthrough protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output.
SC1470
Features
Constant on-time for fast dynamic response Programmable VOUT range = 0.5 - VCCA VIN range = 1.8V - 25V DC current sense using low-side RDS(ON) Sensing or RSENSE in source of low-side MOSFET for greater accuracy Resistor programmable frequency Cycle-by-Cycle current limit Digital soft-start Combined EN and PSAVE functions Over-voltage/under-voltage fault protection and PGOOD output 5uA typical shutdown current Low quiescent power dissipation 14 Lead TSSOP package Industrial temperature range 1% Internal reference Integrated gate drivers with soft switching Efficiency > 90%
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
1.8V - 25V
+5V + R1 C1 + C2
D1 R2 +5V +5V R3 1 2 3 4 5 6 7 C6 SC1470 Q2 U1 BST EN/PSV DH TON LX VOUT ILIM VCCA VDDP FBK PGOOD DL GND PGND 14 13 12 11 10 9 8 Q1 C3 L1 0.5V - 5.5V
PGOOD C5
R4 D2 + C4
R5
R6
Revision: October 14, 2004
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SC1470
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Pin Combination TON to AGND DH, BST to AGND LX to AGND AGND to PGND BST to LX VCCA, VDDP to AGND FB, PGOOD, EN/PSV, ILIM, VOUT, DL to PGND Thermal Resistance, Junction to Ambient(4) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V C/W C C C
JA TJ TSTG TLEAD
100 -40 to +125 -65 to +150 300
Electrical Characteristics
Test Conditions: VIN = 15V, EN/PSV = 5V, VCCA = VDDP = 5.0V, VOUT = 1.8V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter
Conditions Min
25C Typ Max
-40C to 85C Min Max
Units
Input Supplies VCCA Input Voltage VDDP Input Voltage VIN Input Voltage VDDP Operating Current VCCA Operating Current TON Operating Current Shutdown Current Vin = 1.8V - 25V, Offtime > 800ns FB > regulation point, ILOAD = 0A FB > regulation point, ILOAD = 0A RTON = 1M (300kHz) 1.8 1 700 15 -5 5 0 -10 10 1 5.0 5.0 25 5 1100 4.5 4.5 5.5 5.5 V V V A A A A A A
EN/PSV = 0V VC C A VDDP + VIN
Controller Error Comparator Threshold (FBK Turn-on Threshold)(1) Output Voltage Range VCCA = 4.5V to 5.5V Adjust Mode 0.500 0.495 0.5 0.505 VC C A V V
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SC1470
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VIN = 15V, EN/PSV = 5V, VCCA = VDDP = 5.0V, VOUT = 1.8V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter Conditions Min On-Time RTON = 1M Vo = 5V (300KHz) 25C Typ 1140 630 400 VCCA, VDDP = 4.5V to .5V Vin = 4.5V to 25V ILIM - PGND = 0V to OC Limit EN/PSV = Open 0.04 0.3 500 -1.0 +1.0 Max -40C to 85C Min 969 536 Max 1311 725 500 ns ns ns %/V % k A Units
RTON = 500K (600KHz) Vo = 5V Minimum Off Time Line Regulation Error Load Regulation Error VOUT Input Resistance FB Input Bias Current Over-Current Sensing ILIM Sink Current Current Comparator Offset PSAVE Zero-Crossing Threshold Fault Protection Current Limit (Positive) (Note 2) PGND-LX, RILIM = 5K PGND-LX, RILIM = 10K PGND-LX, RILIM = 20K Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGOOD Low Output Voltage PGOOD Leakage Current PGOOD UV Threshold PGND-LX With respect to internal reference. With respect to internal reference. FB forced above OV Vth Sink 1mA FB in regulation, PGOOD = 5V With respect to internal reference. PGND - LX, EN/PSV = 5V DL High PGND - ILIM
10
9.0 -5
11.0 5
A mV
5
mV
50 100 200 -140 -30 +10 2.0
40 90 180 -200 -40 +8
60 110 220 -100 -25 +12
mV mV mV mV % % s
0.4 1 -10 -12 -8
V A %
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SC1470
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VIN = 15V, EN/PSV = 5V, VCCA = VDDP = 5.0V, VOUT = 1.8V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter
Conditions Min
25C Typ 2.0 4.0 165 Max
-40C to 85C Min Max
Units
PGOOD Fault Delay VCCA Undervoltage Threshold Over Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage Enable/Psave Input Resistance Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Dead Time DL Pull-Down Resistance DL Pull-Up Resistance DH Pull-Down Resistance DH Pull-Up Resistance DL Sink Current DL Source Current DH Sink Current DH Source Current
FB forced outside PGOOD window. Rising Edge Hysteresis 100mV 10OC Hysteresis
s 3.7 4.3 V C
EN/PSV low EN High, PSV low (Pin Floating) EN/PSV high R Pullup to VCCA R Pulldown to AGND 1.5 1 2.0 1.2 2.4
1.2 2.4
V V V M M
EN/PSV high to full current limit. SMPS Turn-On
1.6 2
ms ms
DH or DL rising DL low DL high DH low, BST - LX = 5V DH high, BST - LX = 5V DL - PGND = 2.5V VDDP - DL = 2.5V DH - LX = 2.5V, B S T - LX = 5V BST - DH = 2.5V, B S T - LX = 5V
30 0.8 2 2 2 2 1 1 1 1.6 4 4 4
ns A A A A
Notes: (1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. (4) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
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SC1470
POWER MANAGEMENT Pin Configuration
Top View
EN/PSV 1 TON VOUT VCCA FBK PGOOD AGND 2 3 4 5 6 7 14 13 12 11 10 9 8 BST DH LX ILIM VDDP DL PGND
Ordering Information
DEVICE
(1)
PACKAGE TSSOP-14 TSSOP-14 EVALUATION BOARD
SC1470ITSTR SC1470ITSTRT(2) S C 1470E V B
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free option. This product is fully WEEE and RoHS compliant.
TSSOP-14
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 Pin Name EN/PSV TON VOUT VC C A FB K PGOOD AGND PGND DL VD D P ILIM Pin Function Enable/Power Save input . Tie to ground to disable SMPS. Tie to +5V to enable SMPS and activate PSAVE mode. Float to enable SMPS and activate continous conduction mode. On-time set input. Sets on-time of upper MOSFET via series resistor to the input supply. Output voltage sense input. Connect to the output of the SMPS. Supply voltage input for the analog supply. Connect through an RC filter to +5V. Feedback input. Connect from a resistor divider at output of the SMPS to select output voltage. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay following power up. Analog ground. Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive.
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12 13 14
LX DH BST
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SC1470
POWER MANAGEMENT Block Diagram
VCCA VBAT 1 EN/PSV
VCCA POR/SS OT 14 BST HI 2 VIN TON ON OFF PWM CONTROL LOGIC 13 DH 12 LX
VDDP
VBAT
VOUT
+5V
VOUT
3 VOUT 4 VCCA TOFF 1.5V
REF OC ISENSE ZEROI 11 ILIM
FB
FBK
5 FBK
X3
+ PWM +5V
10 VDDP 6 PGOOD 7 AGND FAULT MONITOR OV UV REF + 10% REF - 10% REF - 30% LO 9 DL 8 PGND
FIGURE 1
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SC1470
POWER MANAGEMENT Applications Information
+5V Bias Supply The SC1470 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951A. There are two inputs for the external +5V bias supply, VCCA & VDDP. The VCCA input powers the analog section of the SC1470 while the VDDP input provides power to the upper and lower gate drivers. VCCA will need to be decoupled from the VDDP supply through a 10 ohm resistor and the addition of a filter capacitor from VCCA to ground. The battery input VIN and the +5V inputs VCCA & VDDP can be tied together if the input voltage is fixed from +4.5V to +5.5V; however, as before, VCCA will need to be decoupled from the VDDP supply through a 10 ohm resistor and the addition of a filter capacitor from VCCA to ground. Pseudo Fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitors ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time to 400ns typically. On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input proportional current is used to charge an internal on-time capacitor. The TON time is the time required for the voltage on the capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator. RTON is a resistor connected from the input supply to the TON pin. The graph on page 16 shows the relationship between RTON and switching frequency. Enable & Psave The SC1470 combines the ENABLE and PSAVE functions into a single pin. When the pin is tied to ground the SMPS is disabled. When it is tied to +5V the SMPS is enabled and PSAVE is active. In order to enter PSAVE, the SC1470 PSAVE comparator will look for 8 consecutive inductor current reversals. When this happens, the controller will switch into PSAVE mode. At the same time, the SC1470 will increase the on-time by 1.5 times its set value. This will increase the ripple current and ripple voltage by 1.5 times their continuous conduction mode (CCM) values. This increase has two benefits. First, the reduction in switching frequency will improve efficiency. Second, hysteresis is added to the PSAVE circuit. This is important because when in PSAVE, the very first time a current reversal does not occur, the SC1470 will exit the PSAVE mode. This allows the device to rapidly respond to transient load conditions, while adding hysteresis to eliminate false PSAVE exits. When the pin is left floating, the pin is internally pulled to 2V, enabling the SMPS in CCM. Output Voltage Selection Output voltage selection is set by the feedback resistors R2 & R3 of Figure 3. The internal reference is 1.5V, and the external feedback pin is multiplied by 3 to match the 1.5V reference. Therefore the output can be selected to a minimum of 0.5V. The equation for selecting the output voltage based on Figure 3 is:
R2 Vout = 1 + *0.5 R3
Current Limit Circuit Current limiting of the SC1470 can be accomplished in two ways. First, the device can implement on-state resistance of the low-side MOSFET as the current sensing element (RDSON sensing). Second, the device can accept a resistive element in the low-side source (RSENSE, resistor sensing). The second method offers greater accuracy of the current limit threshold over RDSON sensing, at the added expense of a sense resistor and associated efficiency loss.
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V TON = 3.3x10 -12 *(RTON + 37x10 3 ) * OUT V IN
+ 50S
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
Whether RDSON sensing or RSENSE resistor sensing is used, a scaling resistor between LX and ILIM is required. This resistor, RILIM, is connected to a 10uA current source within the SC1470 through the ILIM pin. This sets a voltage drop equal to 10uA times RILIM. As the current increases through the lower MOSFET, the phase pin voltage will decrease until the offset voltage caused by RILIM is reached and ILIM < PGND. At this point an over-current trip signal is issued. Current limiting will prevent the firing of a DH on-pulse, thereby reducing the switching frequency. As the frequency decreases, the output voltage will drop until an under-voltage shutdown is reached. The current sensing circuit actually limits the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
IL OC (Valley ) = 10A * RILIM RDS ON
IL 2
+5V +VIN
D1
+
C1
Q1 C2 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 L1 0.5V - 5.5V
R1 D2 Q2 + C3 FBK
R2
SC1470
R3
FIGURE 3
The schematic of RDSON sensing circuit is shown in Figure 3 with RILIM = R1 and RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current will be issued. The over-current equation when using an external sense resistor is:
IL OC (Average) = IL OC (Valley ) +
INDUCTOR CURRENT
IPEAK ILOAD ILIMIT
IL OC (Valley ) = 10A *
RILIM R SENSE
Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R4.
+5V +VIN
D1
+
C1
TIME Valley Current-Limit Threshold Point
BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 C2
Q1 L1 0.5V - 5.5V
FIGURE 2
Q2 D2 R1 R4 + C3 FBK
R2
SC1470
R3
FIGURE 4
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
Power Good Output Power good is an open-drain output and requires a pullup resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during startup and will not be allowed to transition high until the output reaches 90% of its set voltage. There is a slight delay built into the PGOOD circuit to prevent false transitions. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the UV protection circuit to prevent false transitions. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.1V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.0V the output drivers are shutdown and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
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The high-side gate driver is equipped with turn-on soft switching to reduce gate drive power dissipation. When a DH turn-on is initiated the pull-up resistance is 10 ohms. This limits the peak high-side gate current before the MOSFET is conducting current. The peak gate current plays a large role in gate driver switching losses. When the high-side MOSFET begins conducting, and LX starts to rise, the pull-up resistance on DH changes to 2 ohms. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process.
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
Design Example The following design example is for the evaluation board schematic shown on page 18. This design will have an input voltage from 4.5V to 19V with an output voltage of 2.5V at 6A. Inductor Selection The switching frequency is set to 300KHz which yields a good trade-off of size and efficiency. RTON is chosen to be 1M Ohm for a switching frequency of 300KHz. Because ripple voltage is used as the feedback mechanism of this device, this leads to the choice of the ripple current being 30% of load current. This will give an nice ripple voltage waveform for ensuring proper PWM triggering for this type of controller. calculate to the same 10K ohm ILIM resistor. However, the power rating of the sense resistor will be 6 * 6 * 0 . 012 = 0 . 432 W affecting the efficiency budget. Output Capacitor Selection The output filter capacitor must have low effective series resistance (ESR) to meet the output ripple and load transient requirements, at the same time have high enough ESR to satisfy stability requirements. In addition, the value of output capacitance must be high enough to absorb the inductor energy going from full-load to noload without tripping the overvoltage protection circuit. For CPU load transients, how much ESR needed depends upon output voltage variation limits under a CPU load transient. The ESR for this condition is given:
IL = 0.3 * 6 = 1.8A
L= VOUT * (VIN - VOUT ) * T VIN * IL
ESR =
VOUT ILOAD(MAX)
L = 4H
Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current. The valley of the inductor current occurs at:
In non CPU applications, the output capacitor size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. Under these conditions the ESR value is given:
ESR =
ILoad(Max) -
IL 2
VOUT(p - p) ILOAD(MAX)
,(see Figure 2) therefore:
IL 2 The inductor must not saturate under all conditions of operation. If the current limit is set to 8.5A the maximum current through the inductor will be: ILIM(Low) > ILoad(Max) -
However, for most CPU applications the minimum capacitance required is limited by the energy absorption of the output capacitor. The equation for determining the minimum capacitance can be found by the following equation:
8.5 + IL = 10.3 A
Setting the over current to 8.5A is calculated as follows:
RDSON*ILOC RILIM = 10A
CMIN =
LOUT *IOUT 2 VF 2 - VI2
RDSON of the MOSFET is a nominal 0.01 ohms, accounting for increased temperature effects use 0.012 ohm.
RILIM = 0.012 * 8.5 = 10K 10A
The inductor chosen was a Panasonic 4uH, 11A inductor. Similarly, using a Sense resistor to obtain a more accurate current limit would make use of the valley current equation. Thus, for a 0.012 Ohm resistor the RILIM would
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Where VF is the final output voltage after release of the load and VI is the initial voltage prior to the release of load. If no more than 100mV of output voltage variation is required between VF and VI , plugging in the numbers for the application circuit yields minimum output capacitance of 1400uF. As shown, a large amount of capacitance is required to absorb the energy of the inductor during a load release of 6A. In typical DDR memory applications a load release of this magnitude is not an issue and therefore the application circuit can get by with 300uF of output capacitance.
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
Stability Considerations: Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a capacitor across the upper feedback resistor divider network. This is shown below in Figure 5, by capacitor C4 in the schematic. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed.
+5V +VIN
SC1470 ESR Requirements Constant on-time control used in the SC1470 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Referring to Figure 5, the equation for the minimum ESR as a function of output capacitance, switching frequency and duty cycle is;
Fs - 200000 1 +3 * Fs R2 +R3 * ESR > R3 2* *Cout *Fs * 1 -D 2 ( )
D1
+
C1
C2 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8
Q1 L1 0.5V - 5.5V
R1 D2 Q2 + C3 FBK
R2
C4 10pF
SC1470
Where D = Vout/Vin. Plugging in the numbers for this design ESR > 0.023 ohms. With the capacitors chosen the total ESR of 0.025 ohms plus the board trace resistance meet the requirement. Input Capacitor Selection Input capacitors are selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows:
IRMS = VOUT * (VIN - VOUT ) * IOUT VIN
R3
FIGURE 5
Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is sign that the ESR should be increased.
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Therefore, for a maximum load current of 6.0A , the input capacitors should be able to safely handle 3A of ripple current. For the EVAL board, we chose two 10uF, 25V ceramic capacitors. Each capacitor has a ripple current capability of 2A.
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
MOSFET Switch Selection The current selection of MOSFETs are determined by the setting of the over-current limit circuit and the maximum input voltage. The next step is to determine their power handling capability. For the EVAL board the IRF7805 & IRF7807 meet the voltage and current requirements. These are 30V, 10A & 7A FET's, respectively. Based on 85C ambient temperature, 150C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 150C; TA = 85C; ja = 50C/W
PT = TJ - TA 150 - 85 = = 1.3W JA 50
VOUT PDLC = 1 *ILOAD2 *RDS(ON) VIN(MAX)
Adding up the power dissipation for each MOSFET can now proceed and the total for each MOSFET should not exceed 1.3W which was calculated earlier to be the maximum power dissipation under worst-case conditions. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 500nS (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200KHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY = TON(MIN) TON(MIN) + TOFF(MAX)
Each FET must not exceed 1.3W of power dissipation. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case conduction power dissipation occurs at minimum battery voltage:
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. Layout Guidelines As with any high frequency switching regulator, it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible. Properly decoupling lines that pull large currents in short periods of time. To keep loop area small always use a ground plane and if possible split the plane in two areas, signal GND and power GND, then tie the two together at one point. Be sure that high current paths have low inductance by making trace widths wide where possible. The SC1470 pin-outs contain digital signals on the right and analog signals on the left side of the device. This facilitates the isolation of digital and analog signals enabling effective layout of the device. In summary follow these guidelines for good PC board layout:
PDUC =
VOUT *ILOAD2 *RDS(ON) VIN(MIN)
Typically, a small high-side MOSFET is selected to reduce switching losses at high input voltages. However, the RDS(ON) limits how small the MOSFET can be. Another element of loss in the upper MOSFET is the switching loss, especially at high input voltages, those seen when the AC adaptor is applied. The upper MOSFET switching losses can be estimated as follows:
PDUS =
CRSS* VIN(MAX )2 * f *ILOAD IGATE
Where CRSS is the reverse transfer capacitance of the upper MOSFET and IGATE is the peak gate-drive source/ sink current which is approximately 1A for the SC1470. For the low-side MOSFET the there are only conduction loses to be concerned about since the commutation diode is active while the lower MOSFET switches. The worstcase power dissipation occurs at maximum battery voltage:
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* Keep high-current paths short, especially at the ground
terminals.
* Tie AGND and PGND together close to the IC. * Keep the power traces and load connections short.
This practice is essential for high efficiency. Using thick copper PC boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more.
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SC1470
POWER MANAGEMENT Applications Information (Cont.)
* Connect the ILIMIT resistor as close to the lower The output inductor value may change with current.
MOSFET drain as possible, and keep the resistance distance from the ILIM pin to the drain short. This will improve current limit accuracy. 1470 System DC Accuracy Three IC parameters affect system DC accuracy, the internal band gap reference, the error comparator offset voltage, and the switching frequency variation with line and load. The internal 1% 1.5V reference contains two error components, a 0.5% DC error and a 0.5% supply and temperature error. The error comparator offset is trimmed so that it trips when the feedback pin is nominally 0.5 volts +/-1% at room temperature. The comparator offset trim compensates for any DC error in the reference. Thus, the percentage error is the sum of the reference variation over supply, temperature and the offset in the error comparator or 1.5%. The on pulse in the SC1470 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on-time regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mV with VIN = 6 volts, then the measured DC output will be 2.525 volts. If the ripple increases to 80mV with VIN = 25 volts, then the measured DC output will be 2.540V. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. This will change the output ripple and thus the DC output voltage. Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = VCCA * IVCCA + Vg * Q g * f
W
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85C JA = 100C/W VCCA = 5V IVCCA = 1100A (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz gives us:
TJ = 85 + 5 * 1100 * 10 -6 + 5 * 60 * 10 -9 * 300 * 10 3 * 100 = 95
(
)
C
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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SC1470
POWER MANAGEMENT Typical Characteristics
SC1470EVB Efficiency at Vout = 1.8V
100 90 Efficiency (%) Efficiency (%) 80 70 60 50 40 30 20 0.001 0.01 0.1 1 2 3 4 5 6 VIN = 25V VIN=14V VIN=4.5V 100 90 80 70 60 50 40 0.001 0.01 0.1 1 2 3 4 5 6 VIN=25V VIN=14V VIN=4.5V
SC1470 Efficiency at Vout = 3.3V
Output Current (Amps)
Load Current (Amps)
SC1470EVB Load Regulation at Vout = 1.8V
0.3 0.2 Load Regulation (%) 0.1 0 -0.1 0 -0.2 -0.3 -0.4 -0.5 -0.6 Load Current (Amps) 1 2 3 4 5 6 Load Regulation (%) Vin = 25V Vin = 19V Vin = 14V Vin = 10V Vin = 4.5V 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 0
SC1470 Load Regulation at Vout = 3.3V
VIN=25V VIN=19V VIN=14V VIN=10V VIN=4.5V 1 2 3 4 5 6
Load Current (Amps)
SC1470EVB Line Regulation at Vout = 1.8V
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 4.5 10 14 Line Voltage (Volts) 19 25 1.2 IL = 1A IL = 2A IL = 3A IL = 4A IL = 5A IL = 6A Line Regulation (%) IL = 0A 1 0.8 0.6 0.4 0.2 0 4.5
SC1470 Line Regulation at Vout = 3.3V
Line Regulation (%)
IOUT=0A IOUT=1A IOUT=3A IOUT=4A IOUT=5A IOUT=6A
10
14 Input Voltage (Volts)
19
25
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SC1470
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Release 6A - 0A, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V, Load Applied 0A - 6A, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V,
0A - 6A Transient, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V
Forced Continuous Mode to PSAVE Mode
Upper Trace: Inductor Current Lower Trace: Phase Lead
Upper Trace: Inductor Current Lower Trace: Phase Lead
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SC1470
POWER MANAGEMENT Typical Characteristics Cont.
Load Step: 0A to +2A, Forced Continuous Mode L = 4uH, Cout = 300uF, Vout = 2.5V, Vin = 15V Load Step: 0A to -2A, Forced Continuous Mode L = 4uH, Cout = 300uF, Vout = 2.5V, Vin = 15V
Frequency vs Input Voltage (Iout = 1A, Vout = 2.5V, Rton = 1M)
310 Frequency (kHz) Frequency (kHz) 300 290 280 270 260 250 5 10 15 Input Voltage (Volts) 20 25 300 290 280 270 260 250 0
Frequency vs Load Current (Vin = 15V, Vout = 2.5V, Rton = 1M)
1
2
3
4
5
6
Load Current (Amps)
Rton vs Frequency (Vin = 15V, Vout = 2.5V, Iout = 1A)
600 Frequency (kHz) 500 400 300 200 100 0 400 500 600 700 800 900 1000 1500
Rton (kohms)
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SC1470
POWER MANAGEMENT Reference Design
4.5V - 25V C1 10uF/25V R1 1M +5V_RUN R2 10 D1 ZHCS400 C2 10uF/6.3V
+5V
C3 0.1uF U1 R3 1M 1 2 3 4 5 6 7 C7 1000pF EN/PSV TON VOUT VCCA FBK PGOOD GND BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8
C4 0.1uF
Q1 Si4818DY
2 R4 C5 0.01uF 10K 1 5 6 7 4
PGOOD C6 1uF
SC1470
3
8
L1 2.5V_SUS 4.1uH + C8 150uF
C9 10uF/6.3V
R5 20K
R6 4.99K
VIN = 4.5V - 25V VOUT = 2.5V; IOUT = 3A
Reference Design Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qty. 1 2 2 1 1 1 1 1 1 1 2 1 1 1 1 1 Reference C1 C2,C9 C3,C4 C5 C6 C7 C8 D1 L1 Q1 R1,R3 R2 R4 R5 R6 U1
17
Part 10uF/25V 10uF/6.3V 0.1uF 0.01uF 1uF 1000pF 150uF ZHCS400 4.1uH S i 4818D Y 1M 10 10k 20k 4.99k S C 1470
Manufacturer
Semtech P/N: SC1470
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2004 Semtech Corp.
SC1470
POWER MANAGEMENT Evaluation Board Schematic
TP1 +5V 1 TP2 GND 1 J1 VIN C1 10uF/6.3V +5V
1 2 C2 10uF/25V R1 1M C3 10uF/25V C4 0.01uF
R2 10 D1 ZHCS400
C5 0.01uF
TP3 EN/PSV 1
Q1 IRF7807 5 6 7 8
SP2
SP1
+5V TP4 PGOOD 1
C6 0.1uF U1 R4 10K 1 2 3 4 5 6 7 EN/PSV BST TON DH VOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND SC1470 14 13 12 11 10 9 8
R3 0
C7 4 0.1uF 1 2 3 L1 4uH D3 ZHCS400 5 6 7 8 5 mOhm C12 10uF/6.3V + C9 150uF + C10 10uF/6.3V R7 NO POP 5 mOhm R8 4.99K C15 NO POP R6 20K 1 2 D2 MBRS140
J2
VOUT
2.5V / 6A
C13 0.1uF
C14 1000pF
R5 10K 4
C11 NO POP
Q2 IRF7805 1 2 3
+ C8 150uF
+5V SW1 2 1 3 ENABLE & PSAVE ENABLE & CCM DISABLE
C16 NO POP
R9 NO POP
R10 0
ET03MD1ABE TP5 1 VCC_SEL
Q3 NO POP
R11 NO POP
Evaluation Board Gerber Plots GROUND
SILK SCREEN
BOTTOM
TOP
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SC1470
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Qty. 3 2 2 3 2 7 1 2 1 2 1 1 1 1 1 2 2 1 1 2 1 5 1 Reference C1,C10,C12 C2,C3 C4,C5 C6,C7,C13 C 8, C 9 Q3,R7,R9,R11,C11,C15,C16 C 14 D1,D3 D2 J1,J2 L1 Q1 Q2 R1 R2 R3,R10 R4,R5 R6 R8 SP1,SP2 SW1 TP1,TP2,TP3,TP4,TP5 U1 Part 10uF/6.3V 10uF/25V 0.01uF 0.1uF 150uF NO POP 1000P f ZHCS400 MBRS140 Banana Jack 4uH IRF7807 IRF7805 1M 10 0 10K 20K 4.99K Probe Test Point ET03MD1ABE P o st S C 1470 Semtech P/N: SC1470 Manufacturer
2004 Semtech Corp.
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SC1470
POWER MANAGEMENT Marking Information Top Mark Bottom Mark
yy = two-digit year of manufacture ww = two-digit week of manufacture
xxxxxx = Wafer Lot Number xx = Assembly Lot Number
Outline Drawing - TSSOP-14
A D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.047 .006 .002 .042 .031 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 0 8 .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0 8 0.10 0.10 0.20
2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 B E
e
aaa C SEATING PLANE
D A2 A H GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW SEE DETAIL L c
C bxN bbb
A1 C A-B D
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1.
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SC1470
POWER MANAGEMENT Land Pattern - TSSOP-14
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp. 21 www.semtech.com

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